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load_queue: an LR waits for committed stores to drain, as an AMO does #74

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load_queue: an LR waits for committed stores to drain, as an AMO does #74

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ef3ae3a
frontend: dispatch takes btb_correct_non_jalr from the queue's packet
adambagley Oct 17, 2026
8080da6
cache: the adapter takes the cached read request at its last LUT
adambagley Oct 17, 2026
5e2d6db
load_queue: an LR waits for committed stores to drain, as an AMO does
adambagley Oct 17, 2026
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18 changes: 10 additions & 8 deletions hw/rtl/cpu_and_mem/cpu/cpu_ooo/cpu_ooo.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -153,6 +153,11 @@ module cpu_ooo #(
// launch cycle. Cached AMOs run at the ROB head.
output logic [riscv_pkg::MemDataBits-1:0] o_data_mem_cached_wr_data,
output logic o_data_mem_cached_read_enable,
// The cached read enable split on its late term, the live LQ launch:
// enable == (sel ? if_sel : if_clear), with early cofactors.
output logic o_data_mem_cached_read_sel,
output logic o_data_mem_cached_read_if_sel,
output logic o_data_mem_cached_read_if_clear,
// Slot id of a cached read (several may be in flight); the adapter tags
// its responses with it and holds a response while a fast-tier response
// is using the LQ response port.
Expand Down Expand Up @@ -1049,7 +1054,6 @@ module cpu_ooo #(
c.btb_predicted_taken = d.btb_predicted_taken;
c.is_ras_return = d.is_ras_return;
c.is_ras_call = d.is_ras_call;
c.btb_correct_non_jalr = d.btb_correct_non_jalr;
c.has_int_dest = d.has_int_dest;
c.has_fp_dest = d.has_fp_dest;
c.uses_int_rs1 = d.uses_int_rs1;
Expand Down Expand Up @@ -1102,7 +1106,6 @@ module cpu_ooo #(
producer_ctrl.btb_predicted_taken = decoded_packet.btb_predicted_taken;
producer_ctrl.is_ras_return = decoded_packet.is_ras_return;
producer_ctrl.is_ras_call = decoded_packet.is_ras_call;
producer_ctrl.btb_correct_non_jalr = decoded_packet.btb_correct_non_jalr;
producer_ctrl.has_int_dest = decoded_packet.has_int_dest;
producer_ctrl.has_fp_dest = decoded_packet.has_fp_dest;
producer_ctrl.uses_int_rs1 = decoded_packet.uses_int_rs1;
Expand Down Expand Up @@ -1145,7 +1148,6 @@ module cpu_ooo #(
producer_ctrl_2.btb_predicted_taken = decoded_packet_2.btb_predicted_taken;
producer_ctrl_2.is_ras_return = decoded_packet_2.is_ras_return;
producer_ctrl_2.is_ras_call = decoded_packet_2.is_ras_call;
producer_ctrl_2.btb_correct_non_jalr = decoded_packet_2.btb_correct_non_jalr;
producer_ctrl_2.has_int_dest = decoded_packet_2.has_int_dest;
producer_ctrl_2.has_fp_dest = decoded_packet_2.has_fp_dest;
producer_ctrl_2.uses_int_rs1 = decoded_packet_2.uses_int_rs1;
Expand Down Expand Up @@ -1189,7 +1191,6 @@ module cpu_ooo #(
producer_ctrl_next.btb_predicted_taken = decoded_packet_next.btb_predicted_taken;
producer_ctrl_next.is_ras_return = decoded_packet_next.is_ras_return;
producer_ctrl_next.is_ras_call = decoded_packet_next.is_ras_call;
producer_ctrl_next.btb_correct_non_jalr = decoded_packet_next.btb_correct_non_jalr;
producer_ctrl_next.has_int_dest = decoded_packet_next.has_int_dest;
producer_ctrl_next.has_fp_dest = decoded_packet_next.has_fp_dest;
producer_ctrl_next.uses_int_rs1 = decoded_packet_next.uses_int_rs1;
Expand Down Expand Up @@ -1233,7 +1234,6 @@ module cpu_ooo #(
producer_ctrl_next_2.btb_predicted_taken = decoded_packet_next_2.btb_predicted_taken;
producer_ctrl_next_2.is_ras_return = decoded_packet_next_2.is_ras_return;
producer_ctrl_next_2.is_ras_call = decoded_packet_next_2.is_ras_call;
producer_ctrl_next_2.btb_correct_non_jalr = decoded_packet_next_2.btb_correct_non_jalr;
producer_ctrl_next_2.has_int_dest = decoded_packet_next_2.has_int_dest;
producer_ctrl_next_2.has_fp_dest = decoded_packet_next_2.has_fp_dest;
producer_ctrl_next_2.uses_int_rs1 = decoded_packet_next_2.uses_int_rs1;
Expand Down Expand Up @@ -1360,7 +1360,8 @@ module cpu_ooo #(
end
`endif
// Use the registered shadow for narrow control fields, for timing. It must
// equal those fields in queue_packet; wide payload uses the bypass mux.
// equal those fields in queue_packet; wide payload and
// btb_correct_non_jalr use the bypass mux.
always_comb begin
from_id_to_ex = queue_packet;
from_id_to_ex_2 = queue_packet_2;
Expand Down Expand Up @@ -1398,7 +1399,6 @@ module cpu_ooo #(
from_id_to_ex.btb_predicted_taken = queue_ctrl.btb_predicted_taken;
from_id_to_ex.is_ras_return = queue_ctrl.is_ras_return;
from_id_to_ex.is_ras_call = queue_ctrl.is_ras_call;
from_id_to_ex.btb_correct_non_jalr = queue_ctrl.btb_correct_non_jalr;
from_id_to_ex.has_int_dest = queue_ctrl.has_int_dest;
from_id_to_ex.has_fp_dest = queue_ctrl.has_fp_dest;
from_id_to_ex.uses_int_rs1 = queue_ctrl.uses_int_rs1;
Expand Down Expand Up @@ -1441,7 +1441,6 @@ module cpu_ooo #(
from_id_to_ex_2.btb_predicted_taken = queue_ctrl_2.btb_predicted_taken;
from_id_to_ex_2.is_ras_return = queue_ctrl_2.is_ras_return;
from_id_to_ex_2.is_ras_call = queue_ctrl_2.is_ras_call;
from_id_to_ex_2.btb_correct_non_jalr = queue_ctrl_2.btb_correct_non_jalr;
from_id_to_ex_2.has_int_dest = queue_ctrl_2.has_int_dest;
from_id_to_ex_2.has_fp_dest = queue_ctrl_2.has_fp_dest;
from_id_to_ex_2.uses_int_rs1 = queue_ctrl_2.uses_int_rs1;
Expand Down Expand Up @@ -3249,6 +3248,9 @@ module cpu_ooo #(
.o_data_mem_cached_byte_wr_en(o_data_mem_cached_byte_wr_en),
.o_data_mem_cached_wr_data(o_data_mem_cached_wr_data),
.o_data_mem_cached_read_enable(o_data_mem_cached_read_enable),
.o_data_mem_cached_read_sel(o_data_mem_cached_read_sel),
.o_data_mem_cached_read_if_sel(o_data_mem_cached_read_if_sel),
.o_data_mem_cached_read_if_clear(o_data_mem_cached_read_if_clear),
.o_data_mem_cached_read_id(o_data_mem_cached_read_id),
.o_data_mem_cached_read_no_merge(o_data_mem_cached_read_no_merge),
.o_mmio_read_pulse(o_mmio_read_pulse),
Expand Down
4 changes: 3 additions & 1 deletion hw/rtl/cpu_and_mem/cpu/cpu_ooo/frontend_control/README.md
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Original file line number Diff line number Diff line change
Expand Up @@ -65,7 +65,9 @@ reports any queued unpredicted JALR (`o_indirect_pending`) to the
control-flow serialization stall. Dispatch reads a register copy of the head
bundle rather than the queue RAM, and takes its narrow control fields from a
register (`o_shadow`) loaded a cycle early from ID's next-cycle value
(`o_from_id_to_ex_next`). `cpu_ooo` keeps further copies of the shadow's
(`o_from_id_to_ex_next`). `btb_correct_non_jalr` comes from the head bundle
instead: ID's target compare sets it late in the cycle, and dispatch only
stores it in the branch's RS entry. `cpu_ooo` keeps further copies of the shadow's
source-register fields (from `o_shadow_next`) for the INT and FP RAT lookups
and the register files' commit-bypass compares.

Expand Down
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