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Two exact timing fixes for X3 paths the L2 work left thin - #73
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The decoded-bundle queue's shadow register gives dispatch its narrow control fields a cycle early, loaded from ID's next-edge values. btb_correct_non_jalr was one of them, so ID's branch-target compare, against a predicted target PD assembles in the same cycle, fed the shadow's next-state mux. In the X3's post-opt netlist of the L2 branch, that path (pd_redirect_pc_low_r to out_shadow_q) had +0.053 ns, and a small change in the load queue took it to -0.160 ns: synthesis maps the logic after the compare differently from one netlist to the next. Dispatch only stores the bit in the branch's RS entry, so it now reads it from the queue's packet, which holds the same value in every cycle, and the bit leaves id_dispatch_ctrl_t. The compare then feeds only the ID-to-EX register, which has +0.264 ns. Dispatch sees the same value in every cycle: CoreMark takes 238,683 and 236,187 ticks before and after, and the decoded_bundle_queue bench passes. X3 post-opt closes at WNS +0.011 ns.
cached_tier_adapter records each accepted read in its slot: the valid bit, the slot's join group, and the live, sent and open bits of the group it opens. The request comes from the router, whose accept follows the LQ's launch, which follows the L0 tag lookup, and the group vectors took a clock enable decoded from it. In the X3's post-opt netlist of the L2 branch these paths had +0.089 ns to the group-vector enables and +0.261 ns to the other bits. A small change in the load queue took the enables to -0.152 ns, and with the enables fixed, the next synthesis took the other bits to -0.176 ns. Free slots now sample their join group every cycle, as they already sample the address, so the request no longer reaches the group-vector enables; a free slot's group is never read. The router also presents its cached read enable as a select between two early terms, the live LQ launch being the select. With SPLIT_READ_REQ, which cpu_and_mem sets, the adapter forms each slot's next valid, live, sent and open bits in one LUT whose late inputs are that select and the slot's own line-port term: the response that answers or bypasses the slot, or the line request that sends its group. Simulation checks that the split request equals the enable, and the router's formal target proves it. The adapter checks in every cycle that the accept state follows its unsplit definition and that each LUT's INIT gives the same bit. The adapter bench passes with and without SPLIT_READ_REQ (a new cached_tier_adapter_split entry), and the router bench, the response-mux proofs, ddr_atomic_test, directed_atomics, dma_envelope_lock3, amo_irq_torture_sim and the TestRIG traces pass. Cycles are unchanged: ddr_bench's kernel lines and lq_stale_slot_probe's 3,732,562 cycles match. X3 post-opt closes at WNS +0.011 ns. The LQ-to-adapter paths now have +0.522 ns or more, and the L1D-response-to-adapter paths +0.228 ns or more.
This was referenced Oct 17, 2026
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Two restructures for X3 paths that #68 left with little post-opt slack, so that small unrelated changes no longer push them negative through synthesis variance. The LR/SC fix in the next PR is one such change.
btb_correct_non_jalrfrom the decoded queue's packet instead of its early shadow register, so ID's branch-target compare no longer feeds the shadow's next-state mux.Both are cycle-exact: CoreMark,
ddr_benchandlq_stale_slot_probetake the same cycles as before, and each commit closes X3 post-opt on its own.